About this scholarly article

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer by Matano, T.; Takai, Y.; Takahashi, T.; Sakito, Y.; Takaishi, Y.; Fujisawa, H.; Kubouchi, S.; Narui, S.; Arai, K.; Morino, M.; Nakamura, M.; Miyatake, S.; Sekiguchi, T.; Koyama, K.; Miyazawa, K. is a scholarly article available to read on EtoBox.

Author

Matano, T.; Takai, Y.; Takahashi, T.; Sakito, Y.; Takaishi, Y.; Fujisawa, H.; Kubouchi, S.; Narui, S.; Arai, K.; Morino, M.; Nakamura, M.; Miyatake, S.; Sekiguchi, T.; Koyama, K.; Miyazawa, K.

Publisher

IEEE

Published

2002

Language

EN