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What is Reversible Logic Decomposition Method about?

This conference proceeding presents a new method for synthesizing reversible logic circuits that aims to minimize concurrently the number of gates, their total delay, and the total garbage outputs. Previous work focused on minimizing only one of these factors. The goal is to develop an algorithm that can synthesize multi-output functions in both regular and non-regular structures using a library of reversible gates while optimizing a weighted cost function of these factors.

Author

Ishaq Ghaznavi

Language

EN