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This document describes Laboratory Activity No. 3 on implementing a CMOS NAND gate. It includes the equation, truth table, schematic, netlist, and output graph of a CMOS NAND gate. The equation is F = AB. The truth table shows the output is 1 when inputs A and B are both 0 or when one input is 1 and the other is 0, and the output is 0 when both inputs are 1. The schematic shows the layout of the NAND gate with NMOS and PMOS transistors. The netlist provides further details of the transistor nodes and voltag

Author

Diego Bersabal

Language

EN