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FPGA Logic Synthesis via Reinforcement Learning by jiangsujiangjiaxi is a document available to read on EtoBox.
This paper presents a novel approach to FPGA logic synthesis using reinforcement learning (RL) to create tailored optimization sequences for circuit netlists, significantly improving area efficiency compared to traditional methods. The authors utilize feature-importance analysis with a random-forest classifier to enhance the RL agent
- Author
- jiangsujiangjiaxi
- Language
- EN