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Experiment3 MUX 4 - 1 by sadiya3693 is a document available to read on EtoBox.
What is Experiment3 MUX 4 - 1 about?
The document describes a 4-to-1 multiplexer (MUX) implemented in Verilog, including its module definition and logic assignment for output Y based on select lines S0 and S1. It also includes a test bench module (TB_MUX) that initializes input signals and applies various test cases to verify the functionality of the MUX. The test bench simulates different combinations of inputs and select lines over time intervals to observe the output behavior.
- Author
- sadiya3693
- Language
- EN