About this document
Vedic Mathematics FPGA Binary Squarer by nithint60 is a document available to read on EtoBox.
The document describes a proposed design and FPGA implementation of a binary squarer based on Vedic mathematics. Specifically, it uses the sutra of Ekadhikena Purvena, which means "one more than the previous". This sutra is typically used for finding the square of decimal numbers ending in 5. The proposed squarer generalizes this sutra to binary numbers. It compares the proposed squarer to a duplex squarer for 8, 16, and 32-bit cases, finding that the proposed design saves around 50% area and reduces delay
- Author
- nithint60
- Language
- EN