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Modelling of Source-coupled Logic Gates by M. Alioto; G. Palumbo; S. Pennisi is a Engineering article available to read on EtoBox.

What is Modelling of Source-coupled Logic Gates about?

## Abstract In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single‐pole behaviour. To generalize the results obtained to cascaded gates, the effect of the input rise time and the loading effect of an SCL gate are discussed. The expressions obtained are simple enough to be used for pencil‐and‐paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology. The model has been validated by comparison with extensive simulations using a 0.35‐μm CMOS process. The model agrees well with the simulated results, since in realistic cases the difference is less than 20% both for noise margin and delay. Therefore, the model proposed can be profitably used for pencil‐and‐paper evaluations an

Who reads Modelling of Source-coupled Logic Gates?

Author

M. Alioto; G. Palumbo; S. Pennisi

Publisher

John Wiley and Sons; Wiley (John Wiley & Sons); John Wiley & Sons Inc.; Wiley (ISSN 0098-9886)

Published

2002

Language

EN

Field

Engineering (Physical Sciences)