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What is Low Power Multi-Source TFET 1T DRAM about?

This document presents a simulation study of a multi-source hetero-junction tunnel field-effect transistor (TFET)-based capacitorless one-transistor dynamic random access memory (1T DRAM) aimed at low power applications. The study analyzes the memory functions of writing, holding, and reading using Synopsys TCAD simulations, demonstrating significant improvements in retention time and sense margin at room temperature. The proposed device operates effectively at low gate voltages, making it suitable for ener

Author

swaroop

Language

EN