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What is Efficient 4x4 Braun Multiplier Design about?
The document discusses the design of an efficient Braun multiplier using different logic styles like Gate Diffusion Input (GDI) logic and Complementary Metal Oxide Semiconductor (CMOS). It aims to optimize the performance of the Braun multiplier in terms of power consumption and delay. The Braun multiplier is implemented using a Kogge Stone adder and 45nm technology in Cadence Virtuoso. Simulation results show that the GDI logic style reduces the delay of the Braun multiplier by 42.38% compared to the CMOS
- Author
- Vinicius Lustosa
- Language
- EN