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RRAM IPUs for Efficient DNNs by chetansb2003 is a document available to read on EtoBox.
The document discusses an RRAM-based in-memory processing unit (IPU) designed for efficient deployment of deep neural networks (DNNs) on embedded devices, addressing challenges related to memory access energy costs. The proposed architecture utilizes dynamic voltage-mode multiply-accumulate operations and a single-slope A/D readout scheme to enhance energy and area efficiency, achieving up to 1.2 2b-POps/s/W and 45 2b-TOps/s/mm2. The paper includes details on the circuit architecture, quantized neural netwo
- Author
- chetansb2003
- Language
- EN