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AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow by D. Soudris; I. Pappas; A. Thanailakis; S. Nikolaidis; S. Siskos; K. Tatas; K. Siozios; G. Koutroumpezis; N. Vasiliadis; V. Kalenteridis; H. Pournara is a scholarly article available to read on EtoBox.

What is AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow about?

The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level lowpower techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18μm STM CMOS technology. The prototype supports partial and dynamic reconfiguration. The efficiency of the entire system (FPGA and tools) was proven by comparisons with commercial systems.

Author

D. Soudris; I. Pappas; A. Thanailakis; S. Nikolaidis; S. Siskos; K. Tatas; K. Siozios; G. Koutroumpezis; N. Vasiliadis; V. Kalenteridis; H. Pournara

Publisher

ACM Press

Published

2005

Language

EN