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VLSI Design of Low-Power SAR ADC by Shruti Konwar is a document available to read on EtoBox.
The article discusses the design and VLSI implementation of an 8-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) using Cadence Virtuoso software with a focus on optimizing the power consumption of the comparator. The ADC operates with input voltages of 0.8V and 5V using 90nm and 180nm technology, respectively, achieving speeds of 50Msa/s and 1Gsa/s. The study highlights the importance of low power design in biomedical applications, demonstrating effective performance through va
- Author
- Shruti Konwar
- Language
- EN