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What is Low Power Hybrid Full Adders about?

This article presents five hybrid full adder designs aimed at reducing power consumption in low power parallel multipliers by utilizing NAND gates instead of AND gates. The proposed ALL-NAND array and tree multipliers demonstrate significant reductions in power consumption and transistor count, with slight increases in time delay compared to conventional designs. The study emphasizes the importance of low power designs in the context of increasing demand for portable electronic devices.

Author

morandotti.francesco

Language

EN