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Table of Contents Contents 1 SCOPE 1.1 Purpose 1.2 Documentation Hierarchy 1.2.1 Component and Land Pattern Family Structure 1.3 Performance Classification 1.3.1 Producibility Levels 1.4 Land Pattern Determination 1.5 Terms and Definitions 1.6 Revision Level Changes 2 APPLICABLE DOCUMENTS 2.1 IPC 2.2 Electronic Industries Association 2.3 Joint Industry Standards (IPC) 2.4 International Electrotechnical Commission 2.5 Joint Electron Device Engineering Council (JEDEC) 3 DESIGN REQUIREMENTS 3.1 Dimensioning Systems 3.1.1 Component Tolerancing 3.1.1.1 Solving for Dimension ‘‘Z’’ 3.1.2 Land Tolerancing 3.1.3 Fabrication Allowances 3.1.4 Assembly Tolerancing 3.1.5 Dimension and Tolerance Analysis 3.1.5.1 Tolerance and Solder Joint Analysis 3.1.5.2 Component Dimensions 3.1.5.3 Land Pattern Dimensions 3.1.5.4 Courtyard Determination 3.1.5.5 Land Pattern Naming Convention 3.1.5.6 Padstack Naming Convention 3.1.5.6.1 Basic Land Shape Letters 3.1.5.6.2 Padstack Defaults 3.1.5.6.3 Examples of the Padstack Naming Convention 3.1.5.6.4 Padstack Naming Convention Modifiers 3.1.5.6.5 Padstack Examples Utilizing Modifers 3.1.5.7 Paste Mask for Thermal Tabs 3.2 Design Producibility 3.2.1 SMT Land Pat
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- Author
- IPC (Organisation)
- Publisher
- I P C (Association Connecting Electronics Industries)
- Published
- 2010
- Language
- EN
- ISBN
- 9781580986458
- Category
- nonfiction
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