About this document
Verilog Models for Logic Gates by aryansinghsikarwar123 is a document available to read on EtoBox.
The document outlines an assessment for Verilog modeling, including tasks such as writing models for basic logic gates and verifying their truth tables using both gate level and data flow modeling. It also includes questions on HDL language, Verilog module concepts, data types in Verilog, and the differences between gate level and data flow modeling. Additionally, it requires writing Verilog code for a half adder and half subtractor with a test bench in Modelsim.
- Author
- aryansinghsikarwar123
- Language
- EN