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Design of Sense Amplifier in The High Speed SRAM by A47Vishal Vishwakarma is a document available to read on EtoBox.
What is Design of Sense Amplifier in The High Speed SRAM about?
The paper presents a new latch-type sense amplifier designed for high-speed and low-power SRAM applications, achieving significant improvements over conventional designs. Simulations using TSMC 65 nm CMOS technology demonstrate that the proposed amplifier reduces access latency to 43.4 ps and average power consumption to 17.47 µW. This advancement highlights the potential for enhanced performance in modern microprocessors where SRAM plays a critical role.
- Author
- A47Vishal Vishwakarma
- Language
- EN