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1GS/s 8b Interleaving SAR ADC Design by 765257795 is a document available to read on EtoBox.
This document describes an 8-bit 1GS/s analog-to-digital converter (ADC) that interleaves two 2-bit/cycle successive approximation register (SAR) ADCs. The ADC utilizes segmentation switching and a compact capacitor array layout to achieve high speed and low power consumption while operating from a 1V supply without calibration. It achieves a figure of merit of 24 femtojoules per conversion step and occupies 0.013 square millimeters in a 65 nanometer CMOS process.
- Author
- 765257795
- Language
- EN