About this document
LPDDR4-3200 Layout and Routing Guide by Kaede Matsushma is a document available to read on EtoBox.
1. This document provides routing recommendations for LPDDR4-3200 memory on an i.MX 8M Nano design. Key recommendations include matching signal delays within a certain picosecond range, using vias properly, and including via delay in overall delay calculations. Tables show example delay calculations and matching for various signal nets on an i.MX 8M Nano EVK board design.
- Author
- Kaede Matsushma
- Language
- EN