About this scholarly article

2020 IEEE International Solid- State Circuits Conference - (ISSCC) - 22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process by Chi, Hyung-Joon; Lee, Chang-Kyo; Park, Junghwan; Heo, Jin-Seok; Jung, Jaehoon; Lee, Dongkeon; Kim, Dae-Hyun; Park, Dukha; Kim, Kihan; Kim, Sang-Yun; Park, Jinsol; Cho, Hyunyoon; Lim, Sukhyun; Choi, YeonKyu; Lim, Youngil; Moon, Daesik; Park, Geuntae; Jang, Jin-Hun; Lee, Kyungho; Hwang, Isak; Kim, Cheol; Son, Younghoon; Kang, Gil-Young; Park, Kiwon; Lee, Seungjun; Doo, Su-Yeon; Shin, Chang-Ho; Na, Byongwook; Kwon, Jisuk; Kim, Kyung Ryun; Choi, Hyein; Choi, Seouk-Kyu; Chang, Soobong; Bae, Wonil; Kwon, Hyuck-Joon; Sohn, Young-Soo; Bae, Seung-Jun; Park, Kwang-Il; Lee, Jung-Bae is a scholarly article available to read on EtoBox.

Author

Chi, Hyung-Joon; Lee, Chang-Kyo; Park, Junghwan; Heo, Jin-Seok; Jung, Jaehoon; Lee, Dongkeon; Kim, Dae-Hyun; Park, Dukha; Kim, Kihan; Kim, Sang-Yun; Park, Jinsol; Cho, Hyunyoon; Lim, Sukhyun; Choi, YeonKyu; Lim, Youngil; Moon, Daesik; Park, Geuntae; Jang, Jin-Hun; Lee, Kyungho; Hwang, Isak; Kim, Cheol; Son, Younghoon; Kang, Gil-Young; Park, Kiwon; Lee, Seungjun; Doo, Su-Yeon; Shin, Chang-Ho; Na, Byongwook; Kwon, Jisuk; Kim, Kyung Ryun; Choi, Hyein; Choi, Seouk-Kyu; Chang, Soobong; Bae, Wonil; Kwon, Hyuck-Joon; Sohn, Young-Soo; Bae, Seung-Jun; Park, Kwang-Il; Lee, Jung-Bae

Publisher

IEEE

Published

2020

Language

EN