About this scholarly article

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) - A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive by Jin-Cheon Kim, ; Sang-Hoon Lee, ; Hong-June Park, is a scholarly article available to read on EtoBox.

Author

Jin-Cheon Kim, ; Sang-Hoon Lee, ; Hong-June Park,

Publisher

IEEE

Published

1999

Language

EN