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01 Building Hierarchy by Aldemir Silva is a document available to read on EtoBox.

What is 01 Building Hierarchy about?

This lab focuses on writing RTL descriptions for two modules, my_and2 and my_or2, and constructing a top-level module my_and_or using structural Verilog. Participants will learn to create a project in the Vivado Design Suite, write RTL code for simple gates, and synthesize the design to view the RTL schematic. The lab is designed to be completed in approximately 45 minutes and requires familiarity with the Linux environment for execution.

Author

Aldemir Silva

Language

EN