Can I read System-on-Chip Test Architectures: Nanometer Design for Testability (Volume .) (Systems on Silicon, Volume .) on EtoBox?

System-on-Chip Test Architectures: Nanometer Design for Testability (Volume .) (Systems on Silicon, Volume .) by Laung-Terng Wang, Charles E. Stroud and Nur A. Touba (Eds.) is a nonfiction available to read on EtoBox.

What is System-on-Chip Test Architectures: Nanometer Design for Testability (Volume .) (Systems on Silicon, Volume .) about?

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. <br><br>This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.<br><br>KEY FEATURES<br>* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.<br>* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.<br>* Covers the entire spectrum of VLSI testing and

Who reads System-on-Chip Test Architectures: Nanometer Design for Testability (Volume .) (Systems on Silicon, Volume .)?

Author

Laung-Terng Wang, Charles E. Stroud and Nur A. Touba (Eds.)

Publisher

Elsevier/Morgan Kaufmann Publ

Published

2007

Language

EN

ISBN

9780080556802

Category

nonfiction

Subjects

Engineering, Mathematics, Computer Science