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System Verilog + OVM: Mitigating Verification Challenges & Maximizing Reusability by Prakash Jayaraman is a document available to read on EtoBox.

What is System Verilog + OVM: Mitigating Verification Challenges & Maximizing Reusability about?

This paper explains how, in our endeavor to accomplish an ideal verification platform for our designs using System Verilog and a standard methodology(OVM) plus some in-house ideas over it, helped us to make a more practical and easy to use verification environment. The paper also explains how the addition of a thin layer between the OVM Methodology classes and our project

Author

Prakash Jayaraman

Language

EN