About this document
Low Power VLSI Design Techniques by SanthoshReddy is a document available to read on EtoBox.
This document discusses optimizations for low power VLSI design through architecture mapping. It explores three key techniques: spatial locality, temporal locality, and regularity. Spatial locality involves mapping correlated operations to shared resources to reduce data transfers. Temporal locality reduces register file sizes through scheduling. Regularity identifies repetitive computations that can be implemented with specialized hardware modules or instructions. Two design examples applying these techniq
- Author
- SanthoshReddy
- Language
- EN