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RISC-V SoC Design with FemtoRV32 Core by anitvargheseofc2011 is a document available to read on EtoBox.

This conference paper presents the first physical implementation of a RISC-V core based on the FemtoRV32 project using a Quark core in 180 nm CMOS technology. The implementation achieved a clock frequency of 120 MHz, demonstrating a 150% performance improvement over FPGA prototypes, with power dissipation ranging from 68 to 108 mW. The paper outlines the methodologies and tools used for ASIC development, validating the micro-architecture for potential low-cost microprocessors or custom ASICs.

Author

anitvargheseofc2011

Language

EN