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What is CMOS Inverter and NAND Gate Design Problems about?
This document contains 5 homework problems for an EE 42 class due on Friday, May 7 at 4pm. Problem 1 asks the student to calculate the width of a PMOS transistor (Wp) needed for a CMOS inverter with a midpoint voltage of 2.5V. Problem 2 asks the student to find the output voltage (VOUT) of a circuit with a diode and resistor. Problem 3 asks about the maximum fanout of a CMOS NAND gate given a worst-case propagation delay. Problems 4 and 5 ask the student to determine how changes to transistor dimensions and
- Author
- Shimaa Barakat
- Language
- EN