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This document discusses the design of a low power, high speed multiplier using a low power VLSI precomputation technique called Spurious Power Suppression Technique (SPST). Modified Booth algorithm is used to reduce the number of partial products by half. SPST is applied to the modified Booth encoder and compression tree to filter out useless switching power. Simulation results show SPST implemented with AND gates provides flexibility to adjust data assertion timing, leading to improved speed and reduced po
- Author
- Badrinath Gopendran
- Language
- EN