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Chandan Kumar Challagundla is seeking a career where he can utilize his skills in organizations and learn new skills. He has an M.Tech from NIT Durgapur and a B.Tech from JNTUA College of Engineering. He has work experience as an intern at NXP Semiconductors and Amararaja Electronics. His areas of interest include RTL design, static timing analysis, digital ASIC flow, FPGA design, and analog design. He is proficient in Verilog, Python, Unix, C and has exposure to tools like Vivado, VCS, Xcelium, QuestaSim,

Author

chimp

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EN