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This paper presents a novel high-speed multiplier architecture based on ancient Vedic mathematics, specifically utilizing the Urdhwa Tiryakbhyam Sutra. By incorporating compressor adders, particularly 4:2 and 7:2 compressors, the proposed design achieves nearly double the speed of traditional multiplication methods while reducing area requirements by 1%. The findings indicate significant improvements in processing speed and efficiency, making this approach advantageous for modern processor designs.
- Author
- rao.dwh92
- Language
- EN