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Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model by Jiang Hu; Sachin S. Sapatnekar is a scholarly article available to read on EtoBox.

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We present a simultaneous Buffer Insertion and Non-Hanan Optimization (BINO) algorithm to improve the performance of VLSI interconnect. This algorithm aims to address the realistic situation where both the interconnect resources and timing constraints are stringent and the wire topology is to be optimized using available spaces for buffer insertions after cell placement. These spaces sre fixed relative to the changing routing tree during non-Hanan optimization. The objective here is to minimize weighted sum of wire and buffer cost subject to timing constraints. In BINO, buffer insertion and non-Hanan optimization are conducted simultaneously and iteratively in a greedy fashion till the improvements are exhausted. To assure the accuracy of timing evaluation, the fourth order AWE model is employed. Experimental results on both .18pm IC and MCM technology showed significant cost reductions.

Author

Jiang Hu; Sachin S. Sapatnekar

Publisher

ACM

Published

1999

Language

EN