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What is High-Speed Synchronous Counter Design about?
This document proposes a high-speed synchronous counter design using True Single-Phase Clock (TSPC) based toggle flip-flops (TFFs). Key points: 1) An 8-bit synchronous counter can operate up to 4.54 GHz with 0.67 mW power using the proposed TSPC TFF design in a 0.18 μm CMOS process. 2) The TSPC TFF allows both synchronous up/down counting at positive and negative clock edges. Extended TSPC logic is embedded to realize the combinational carry chain logic. 3) Asynchronous preset and clear inputs are also
- Author
- SMB
- Language
- EN