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Buffering global interconnects in structured ASIC design by Tianpei Zhang; Sachin S. Sapatnekar is a scholarly article available to read on EtoBox.

What is Buffering global interconnects in structured ASIC design about?

Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This paper proposes a novel and accurate statistical estimation technique for distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the estimation for a uniform buffer distribution is accurate and economic.

Author

Tianpei Zhang; Sachin S. Sapatnekar

Publisher

ACM Press

Published

2005

Language

EN