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The document presents a low-power 10 Gb/s receiver utilizing a switched-capacitor summation decision feedback equalization (DFE) designed in 90-nm CMOS technology. It highlights the challenges of interconnect bandwidth scaling and the effectiveness of DFE in mitigating inter-symbol interference (ISI) for short to medium-distance PCB traces while consuming less than 6.0 mW. Key techniques discussed include analog multiplexing, quarter-rate clocking, and the design of a summer circuit to enhance receiver perf
- Author
- d9xzfj8hvb
- Language
- EN