About this document

1 s2.0 S0038110125001765 Main by Sai is a document available to read on EtoBox.

This article investigates the design space and experimental feasibility of Junctionless Forksheet FETs (JL-FSFET) for sub-3 nm technology nodes, focusing on optimizing parameters such as gate length, width, and thickness for improved digital and analog/RF performance. It identifies an optimal design range for gate length and suggests that stacking sheets can enhance performance, although it may compromise certain metrics. The findings indicate significant potential for JL-FSFETs in future device and circuit

Author

Sai

Language

EN