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The document presents a formal analysis of the ACE (AXI Coherency Extension) specification for cache coherent systems-on-chip, detailing its structure, components, and the modeling process using the CADP toolbox. It highlights the importance of system-level cache coherency and the methodologies used for verification, including the LNT specification language and MCL temporal logic. The analysis aims to ensure data integrity and coherency within the ACE-compliant systems, with ongoing work focused on practica
- Author
- sckid
- Language
- EN