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The Xilinx MIG Virtex-6 design uses an internally generated clock to capture the data on DQ during reads. This is beneficial because it is a true free-running clock and has no pre/ post-amble glitches as DQS does. The RSYNC clock is used for final stage data capture in the DQ ISERDES and to transfer read data into fabric.

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thennavan_balu5976

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EN