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This paper presents a mapping methodology for implementing large Boolean logic circuits on memristor crossbars, addressing the limitations of current CMOS technology. It introduces place-and-route schemes and optimization techniques to enhance performance in terms of area, delay, and power consumption. The methodology is demonstrated through a multibit adder and nine additional complex benchmarks, showcasing its applicability and potential for future computer architectures.

Author

Vrsha Solachi

Language

EN