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This document presents a high-efficiency multiply-accumulator (MAC) utilizing ternary logic and approximate algorithms, achieving 30% lower power consumption and only 2% computation error compared to traditional designs. The study demonstrates that ternary circuits can significantly reduce power-delay-product by 74%-80% and improve area efficiency by approximately 45%. The proposed ternary MAC unit is evaluated using both carbon-nanotube and silicon-based technologies, showcasing its potential for practical

Author

Michael Margolese

Language

EN