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A Robust Design of Highly Efficient Dynamic Comparator Using Wave Pipelining by IJARTET is a document available to read on EtoBox.
A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with high speed, low power dissipation and immune to noise than the previous reported work is proposed. As compared to the existing design layout that consists of switching flip-flops, which shows high delay time and more power consumption during operations. In order to avoid these problems there by minimizing delay time and consuming less power. Back to
- Author
- IJARTET
- Language
- EN