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Secure FPGA RISC-V Design Flow by Jeet is a document available to read on EtoBox.

What is Secure FPGA RISC-V Design Flow about?

This paper presents a secure design flow for FPGA-based RISC-V implementations, focusing on mitigating boot time and run-time software attacks through secure boot and Information Flow Tracking (IFT) techniques. The proposed solution utilizes Trusted Platform Module (TPM) for self-authentication and ensures the integrity of firmware during startup while tracking data flow to prevent memory corruption. The implementation aims to enhance security in embedded applications, particularly in the context of Interne

Author

Jeet

Language

EN