About this document
Understanding Guard Rings in CMOS Design by narendra is a document available to read on EtoBox.
This document discusses different techniques used in integrated circuit layout design to isolate devices and prevent latch-up. It describes N-wells, which are deposited to provide an N-type substrate for P-channel devices in a mostly P-type substrate. Taps are inserted into N-wells to drain away charge buildup and control potential. Guard rings are extended tap structures that completely enclose a group of devices to improve isolation. Deep N-wells provide additional isolation for N-channel devices by surro
- Author
- narendra
- Language
- EN