About this document
Projet Mcsl2026 by gggvvvvibu is a document available to read on EtoBox.
The document discusses the design and implementation of a multiplier-less architecture for Finite Impulse Response (FIR) filters using distributed arithmetic. This approach aims to enhance throughput and minimize hardware usage on FPGAs by leveraging Look-Up Tables (LUTs) for precomputed filter coefficients and employing shift-and-add operations. The architecture eliminates the need for conventional multipliers, making it more efficient.
- Author
- gggvvvvibu
- Language
- EN