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This paper discusses the design and implementation of an external scrubbing technique for mitigating Single Event Upsets (SEUs) in rad-tolerant Xilinx Virtex-4 FPGAs used in the Digital Bandwidth Efficient Filter subsystem for the INSAT-3DR payload. The scrubbing engine, implemented using a rad-hard Actel FPGA, refreshes the configuration memory to prevent error accumulation without disrupting system operations. The study includes reliability and availability analyses, demonstrating that periodic scrubbing

Author

Vishwanath Just Rocking

Language

EN