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What is LUT Optimization for Memory Multipliers about?
This document proposes two new techniques to optimize look-up tables (LUTs) used for memory-based multiplication in digital signal processing applications. The first technique reduces the LUT size by half by excluding the sign bit from the LUT address, saving area at the cost of a small overhead. The second technique proposes an anti-symmetric product coding scheme that further reduces the LUT size by half by adding or subtracting a fixed value from the LUT output. Simulation results show the proposed optim
- Author
- btechece65
- Language
- EN