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What is High-Performance Low-Power SRAM Decoder about?

This document details the design and evaluation of mixed-logic address decoders for SRAM arrays using TSMC 28nm CMOS technology, focusing on a hybrid approach that combines pass-transistor logic and CMOS inverters. The results demonstrate significant improvements in propagation delay, power dissipation, and transistor count compared to traditional CMOS decoders. The methodology is scalable and applicable for ultra-low-power VLSI systems.

Author

Chiranjeevi varma P

Language

EN