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320 MS/s Low-Cost SAR ADC Design by 937496067 is a document available to read on EtoBox.
This paper introduces a low-cost 10-bit 320 MS/s successive approximation register (SAR) ADC designed for IEEE 802.11ac applications using 20 nm CMOS technology. The ADC features a binary-scaled recombination capacitor weighting method, achieving low power consumption and high signal-to-noise ratio (SNR) performance. The prototype demonstrates effective resolution bandwidth and occupies a compact active area, making it suitable for high-speed wireless applications.
- Author
- 937496067
- Language
- EN