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What is Low Power 65nm Charge Pump Design about?
This document presents a low power, low noise 65nm charge pump designed for integer or fractional-N PLL applications, achieving a power consumption of 309uW at 1V with a current mismatch below 0.01%. The charge pump incorporates active current mismatch compensation and a smoothing capacitor to enhance linearity and reduce noise. The layout dimensions are 88um x 80um, and the design demonstrates effective performance across a voltage range of 0.3V to 0.75V.
- Author
- Yassen Sayed
- Language
- EN