About this scholarly article

Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic by R. Pandey; H. Madan; H. Liu; V. Chobpattana; M. Barth; B. Rajamohanan; M. J. Hollander; T. Clark; K. Wang; J. H. Kim; D. Gundlach; K. P. Cheung; J. Suehle; R. Engel-herbert; S. Stemmer; S. Datta is a scholarly article available to read on EtoBox.

Author

R. Pandey; H. Madan; H. Liu; V. Chobpattana; M. Barth; B. Rajamohanan; M. J. Hollander; T. Clark; K. Wang; J. H. Kim; D. Gundlach; K. P. Cheung; J. Suehle; R. Engel-herbert; S. Stemmer; S. Datta

Publisher

IEEE

Published

2015

Language

EN