About this document
RISC-V 3x3 Matrix Multiplication Accelerator by 21349ec045 is a document available to read on EtoBox.
The document outlines two design challenges: creating a Mini CNN Compute Unit for CNN operations and a RISC-V based systolic array accelerator for matrix multiplication. Both projects require hardware design and implementation with specific functional requirements, including memory management, arithmetic operations, and integration with RISC-V architecture. Participants must adhere to strict guidelines and deliverables, including documentation, simulation, and performance evaluations, while following propri
- Author
- 21349ec045
- Language
- EN