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This paper presents the design and evaluation of a 16:1 multiplexer and a 1:16 demultiplexer using various adiabatic logics aimed at reducing power consumption in VLSI circuits. It compares the performance of CMOS logic with adiabatic logics such as 2N2P, 2N2N2P, and Dualsleep, highlighting the advantages of lower power dissipation in adiabatic circuits. The results indicate that Dualsleep logic outperforms other adiabatic and traditional logics in terms of energy recovery and power efficiency.

Author

ramavathsruthi12

Language

EN